(a) Technical Field of the Invention
The present invention relates to a phase-frequency detector, and in particular, to a phase-frequency detector with no dead zone used in a phase-locked loop.
(b) Description of the Prior Art
As a result of upgrading network transmission technology and the needs of network users, the data transmission rate is being upgraded continuously. For instance, with regard to the application range of IEEE 1394a, the maximum transmission rate is 400 MHz, and it employs data strobe coding method in data transmission. As shown in FIG. 1, the transmission signal during data transmission includes a data signal and a strobe signal, and when the data is read, the clock signal which is used to recover the data is derived from the result of the exclusive OR operation of the data signal and the strobe signal received by the receiving end (Data XOR Strobe signal).
With respect to the above, during the data transmission and reading data process, a phase-locked loop is employed to generate a stable clock signal. If the phase-locked loop generates a clock signal with undesired jitter, the duty cycle of the clock signal (Data XOR Strobe signal) produced by the receiving end will not be accurate, which will increase the bits error rate of the received data. Thus, during the data transmission and data recovery process, it is very important that the phase-locked loop generates stable clock signals. In other words, for accurate data transmission, the clock signal generated by the phase-locked loop must have very low jitter. The jitter of the clock signal is closely related with the phase-frequency detector in the phaselocked loop.
FIG. 2 illustrates the block diagram of a conventional phase-locked loop 1, which comprises a phase-frequency detector 11, a charge pump 12, a voltage controlled oscillator 13 and a frequency divider 14. The phase-frequency detector 11 receives a reference clock signal CK.sub.ref from the outside and a feedback clock signal CK.sub.vco from the frequency divider 14, compares the phase and the frequency of the two signals, and then outputs the up, dn signals to control the charge pump 12.
The charge pump 12, based on the control signal up, dn output from the above phase-frequency detector 11, provides an appropriate output voltage Vc to the voltage controlled oscillator 13. The voltage controlled oscillator 13, based on the above voltage Vc, outputs a clock signal. The frequency divider 14 receives the clock signal and outputs a feedback clock signal, denoted by CK.sub.vco, with frequency divided by some number. The feedback clock signal is used as the input signal of the phase-frequency detector 11.
With respect to the aforementioned phase-locked loop 1, the phase-frequency detector 11 comprises two D flip-flops 111, 112 and an AND gate 113 (as shown in FIG. 3(a)). The output terminal of the AND gate 113 is connected to the reset 15 terminals of the D flip-flops 111, 112 respectively. With such a structure, if the reference clock signal CK.sub.ref and the feedback clock signal CK.sub.vco shown in FIG. 3(b) are respectively input into the D flip-flops 111, 112, the D flip-flop 111 will theoretically produce a Q.sub.A signal as shown in FIG. 3(b), where the signal CK.sub.ref is ahead of signal CK.sub.vco. Theoretically, only the signal of Q.sub.A is at "1". However, in practice, when signal CK.sub.ref changes from "0" to "1", Q.sub.A will be at "1". When signal CK.sub.vco changes from "0" to "1", Q.sub.B will be at "1" instantaneously. At this moment, the signals Q.sub.A, and Q.sub.B are simultaneously at "1". Thus, the output signals of the D flip-flops 111, 112 are reset, and Q.sub.A, and Q.sub.B will be lowered to "0", which is further explained as follows.
The phase-frequency detector 11 comprises an AND gate 113, due to its delay, the output Q.sub.A and Q.sub.B are both at "1" in a short moment (i.e. the delay time of the AND gate) regardless of the phase difference between the reference clock signal CK.sub.ref and the feedback clock signal CK.sub.vco. At this moment, if the phase difference between CK.sub.ref and CK.sub.vco is very small, and the load of Q.sub.A and Q.sub.B is large, then their signals will attenuate and will not drive the AND gate 113 or transmit the signals, thereby causing misdetection of the signal. In other words, the phase-frequency detector 11 will produce the clock jitter phenomenon. This undetectable range of phase difference is known as a dead zone of the phase-frequency detector 11, which is shown as range .+-.x in FIG. 4.
Accordingly, the scope of the dead zone has to be reduced first in order to reduce the clock jitter.